Micromechanical indentation study of stress related effects in transistor channels

Stress inside the chip results into deviations of the transistor performance due to the piezoresistive behavior of the silicon channels. In this thesis, micromechanical indentation is introduced to study stress effects on the electrical characteristics of CMOS transistors. The approach combines non-destructive indentation to induce well defined localized stress, electrical characterization of ring oscillator circuits under load as well as finite element simulations. The approach enhances the local resolution of stress effect studies in microelectronic samples. During the indentation experiments using spherical tip edges from the backside of thinned silicon chips, the changes of the circuit performance are measured. Subsequently, FE simulation provides the induced stress fields in the device channels parametrized by the loading sequences, chip layouts and tip geometries. Specifically engineered indentation tip geometries are utilized to control the induced stress in order to study directional stress effects on the transistor performance. Based on a set of three independent indentation experiments, the directional piezoresistive coefficients of the device channels are computed.