Leveraging Dark-Silicon for Power-Efficient Real-Time Network-on-Chip Architectures

NoC-based Multi-Cores are appealing as the typical platform uniquely fulfilling the requirements of embedded and cyber physical systems. However, their prominence is restrained by fundamental energy barriers leading to the emergence of the Dark-Silicon era which prevents the simultaneous utilization of the complete chip. This promotes energy efficiency as an outstanding design goal for future NoC-based Multi-Cores, where NoCs significantly contribute to the total chip power. Specifically, real-time NoCs are gaining an utmost attraction since a large expanse of embedded systems are restricted by real-time (RT) constraints. In that context, the work in this dissertation focuses on NoC architectures fitting real-time applications with more concern to energy efficiency in the Dark-Silicon (Dark-Si) era. Although several contributions exist in the literature for energy efficiency in RT-NoCs, none of them tackled the problem from a Dark-Si perspective. In addition, the effect of conventional energy minimization techniques such as voltage-frequency-scaling is fading with the shrinking technology thus calling for new complementary techniques. Furthermore, several architectural solutions are presented in the literature targeting RT-NoCs. However, they lack a common evaluation platform. These untackled research points were the focus of this doctoral thesis. The thesis contributes to the discussed gaps by focusing on how to leverage the Dark-Si existence in real-time NoC architectures for low power and power-density designs. It presents a thorough investigation of RT-NoC architectures on both theoretical and practical levels by conducting for the first time a comprehensive survey on RT-NoCs and implementing a hardware framework for reliable evaluation of RT-NoCs, called ARTNoCs. It further presents two new proposed NoC architectures, DaSiC-NoC and HPPT-NoC to leverage Dark-Si for power-efficient real-time NoC architectures with equal or better predictability performance.