Integration of Multi-Level 1T1R RRAM Cells as Embedded Memory

This thesis proposes a structural approach for integration of one-transistor-one-resistor (1T1R) resistive random access memory (RRAM) cells as embedded memory in integrated circuits. By separating the integration process into three steps with different tasks and focuses, it uses a divide& conquer approach to realize embedded memory for emerging, resistive memory technologies. Besides the overall concept, concrete circuit solution with new read and programming concepts with focus on RRAM's multi-level capability are presented. As the final integration step, fully-differential multi-level cell designs with automatic place and route are proposed for the first time to achieve completely embedded RRAM memory.