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![]( "Buchcover ISBN 9780470824085")
The book all semiconductor device engineers must read to gain apractical feel for latchup-induced failure to produce lower-costand higher-density chips.
Transient-Induced Latchup in CMOS IntegratedCircuits equips the practicing engineer with all thetools needed to address this regularly occurring problem whilebecoming more proficient at IC layout. Ker and Hsu introduce thephenomenon and basic physical mechanism of latchup, explaining thecritical issues that have resurfaced for CMOS technologies. Oncereaders can gain an understanding of the standard practices forTLU, Ker and Hsu discuss the physical mechanism of TLU under asystem-level ESD test, while introducing an efficientcomponent-level TLU measurement setup. The authors then presentexperimental methodologies to extract safe and area-efficientcompact layout rules for latchup prevention, including layout rulesfor I/O cells, internal circuits, and between I/O and internalcircuits. The book concludes with an appendix giving a practicalexample of extracting layout rules and guidelines for latchupprevention in a 0.18-micrometer 1.8V/3.3V silicided CMOSprocess.
* Presents real cases and solutions that occur in commercial CMOSIC chips
* Equips engineers with the skills to conserve chip layout areaand decrease time-to-market
* Written by experts with real-world experience in circuit designand failure analysis
* Distilled from numerous courses taught by the authors in ICdesign houses worldwide
* The only book to introduce TLU under system-level ESD and EFTtests
This book is essential for practicing engineers involved in ICdesign, IC design management, system and application design, reliability, and failure analysis. Undergraduate and postgraduatestudents, specializing in CMOS circuit design and layout, will findthis book to be a valuable introduction to real-world industryproblems and a key reference during the course of theircareers.
Transient-Induced Latchup in CMOS IntegratedCircuits equips the practicing engineer with all thetools needed to address this regularly occurring problem whilebecoming more proficient at IC layout. Ker and Hsu introduce thephenomenon and basic physical mechanism of latchup, explaining thecritical issues that have resurfaced for CMOS technologies. Oncereaders can gain an understanding of the standard practices forTLU, Ker and Hsu discuss the physical mechanism of TLU under asystem-level ESD test, while introducing an efficientcomponent-level TLU measurement setup. The authors then presentexperimental methodologies to extract safe and area-efficientcompact layout rules for latchup prevention, including layout rulesfor I/O cells, internal circuits, and between I/O and internalcircuits. The book concludes with an appendix giving a practicalexample of extracting layout rules and guidelines for latchupprevention in a 0.18-micrometer 1.8V/3.3V silicided CMOSprocess.
* Presents real cases and solutions that occur in commercial CMOSIC chips
* Equips engineers with the skills to conserve chip layout areaand decrease time-to-market
* Written by experts with real-world experience in circuit designand failure analysis
* Distilled from numerous courses taught by the authors in ICdesign houses worldwide
* The only book to introduce TLU under system-level ESD and EFTtests
This book is essential for practicing engineers involved in ICdesign, IC design management, system and application design, reliability, and failure analysis. Undergraduate and postgraduatestudents, specializing in CMOS circuit design and layout, will findthis book to be a valuable introduction to real-world industryproblems and a key reference during the course of theircareers.
